Calculator system having keyboard with double entry protection and serialized encoding

ABSTRACT

Disclosed is a calculator system having a keyboard providing double entry protection. The keyboard comprises an array of keys in rows and columns with the columns strobed in sequence by cycle times of the calculator system. An encoder coupled to the rows of the keys provides encoded representations of particular row actuation upon a specific key depression. Both true and complement representations are provided for preventing double entry. A serializer is responsive to the encoder for serializing the row line representation and the particular cycle time to define the particular key actuated and to define a new instruction memory address. The serialized representation is stored in a memory register in synchronization with subcycle times for eventually addressing an instruction memory.

United States Patent Cochran et al.

i 1 CALCULATOR SYSTEM HAVING KEYBOARD W'ITH DOUBLE ENTRY PROTECTION AND SERIALIZED ENCODING {751 Inventors: Michael .I. Cochran. Richardson;

Charles P. Grant, Jr., Dallas, both of Tex 1731 Assignee: Texas Instruments, Incorporated,

Dallas, Tex.

1221 Filed: Sept. 13, 1973 1211 Appl. No: 396,959

l52| U.S. Cl 235/156; 340/1725; 340/365 E; 340/365 S [51] Int. Cl. .1 C061 3/02 [58] Field of Search .i 235/156, 159 16() 164, 235/153 A; 340/1725 365. 3 E

156] References Cited UNITED STATES PATENTS 3.660.826 5/1972 Lins i i i r H 340/365 E X 3.7IJ(: 973 12/1972 Acquadro ct aim 340/1725 171K746 2/1973 Hatzmu 341N365 S 3.7%,4s7 1/1974 Davis et al 340/365 S Primary Exam1'nerDavid H. Malzahn Almrncyx Again 0r l-'irmHaro1d Levine; Ren E (irossrnan; Thomas G. Devine I 57] ABSTRACT Disclosed is a calculator system having a keyboard providing double entry protection. The keyboard comprises an array of keys in rows and columns with the columns strobed in sequence by cycle times of the calculator system. An encoder coupled to the rows of the keys provides encoded representations of particular row actuation upon a specific key depression. Both true and complement representations are provided for preventing double entry. A serializer is responsive to the encoder for serializing the row line representation and the particular cycle time to define the particular key actuated and to define a new instruction memory address. The serialized representation is stored in a memory register in synchronization with suhcycle times for eventually addressing an instruction memory.

6 Claims. 81 Drawing Figures PATENTED M626 1975 902 O54 SHEET 1 PATENTEDAUBZBIBIS 1902054 SHEET 2 I g g PROGRAMMER 2 CHIP a n n PR INT ER CHIP BUSY

ARITHMETIC CHIP SEG A n"... SEG B rr-r-r-r ffffiuuuwr SEGMENT DRIVERS DIGIT DRIVERS l8 "K" LINES KEYBOARD PATENTED AUBZBIQTE branch Branch of Condition=1 MSB LSB

Relative Branch Address Fig. 5a

=O=INCREMENT =1=DECREMENT SHEET branch OZ O 54 F/g, 5b

MO Fla 1 1g Operatlon M1 A11 Mask M2 DPT MSB M3 DPT 1 M 1 DPT 0 M5 LLSD 1 M6 EXP M7 EXP 1 M3 KEYBOARD OPERATIONS M9 MANT M10 WAIT OPERATIONS M11 MLSD 5 M12 MAEX LSB M13 MLSD 1 .Ml L MMSD 1 J M15 MAhX 1 R0 A N R1 B+N R2 C N MSB R3 O+N Ru Shift A B5 Shift R R6 Shift 6 R7 Shift D R A+B R9 OIB R10 +D R11 AID R12 Aiconstant R13 NO-OP Rl L 0+ Constant LSB J R15 RTE-Adder (Mask LSD) :O:add=shift left :l.r."vub=.lhift right PATENTED M182 61975 O 54 sum 7 The following 8 bits effective only if flag operations 7 (fmd) MSB 16 The following 8 bits effective Generate Fla-gMask only if Keyboard operations when these '4 bits equal y the 4 encoded state 1 bits =O=SCAN KYBD (NOTE: ENCODED STATE TIMES ARE +2 FROM ACTUAL STATES) A =l=KT (fma) LSB- 6 =O=KS The following t bits (flagops) effective only during flavgmask I M & 1 5 ZO=KR o TEST FLAG A =O=KQ 1 TEST FLAG B 7 2 SET FLAG A I I 3 SET FLAG B 2 =O=KP (fd) a ZERO FLAG A MSB 5 ZERO FLAG B I I f l =O=KO l 6 INVERT FLAG A 1" 7 INVERT FLAG B 10 8 EXCH. FLAG A B =O=KN (fb) 9 COMPARE FLAG A B 10 SET FLAG KR ll ZERO FLAG KR F/g', l2 COPY FLAG B+A LSB f 13 COPY FLAG A-B lu REG 5-FLAG A S0 S3 f 15 REG B FLAG B S0 S3 Fig 5c SHEET PATENTEB M182 61975 E E E 2 w llljlzll i zllFi|||P. -il| 1%. 3| w i 5 3 1 I 3 3 m 131-- I 3 1 3 v 1 1 T JM PATENIEU AUGZSlQTS 3. 902 O54 SHEET 1 1 TO DISPLAY ARITHMETIC CHIP 's :qs

SQQQQQ ea 27 26 z: 2 23 2 9/0///2/3/4 l I I I \PPJ Fig, 7

a S01E5 pmgmgmuszsms SHEET 12 Fig. 8b] Fig. 8bZ Fig.8b3 Fig. 8b4 Fig. 8b5

Fig. 8b6 Fig. 8b? Fig. 8b8 Fig. 8b9 Fig. 8b10 Fig. 8c1 Fig. 8c2 Fig. 8c3 Fig. 8::4

Fi 3C5 Fig. 8c6 ig. 8c? Fig. 8c8

Fig, 8d1 Fig. 8d2 Fig. 8d3

Fig. 8d4 Fig. 8d5 Fig. 8d(:

PATENTED AUBZEIQTS SHEET 15 $902,05 PAIENTEU m2 6 ms SHEET 16 Fig. 8b 4 0mm csks 0 1 0 ANYOMD /6 .976 9 SH/Ff D PATENTEI] AUBZ 61975 SHEET 19 Fig. 867

V W v v (a /571) $1.15 Ft q 0 

1. In a calculator system of the type having a permanent store memory for storing and selectively providing instruction words, a keyboard system for generating an address to said instruction memory comprising in combination: a. an array of keys in rows and columns with the columns strobed in sequence by cycle times of the calculator system; b. encoder means coupled to said rows of keys for providing an encoded representation of particular row actuation upon a specific key depression; c. means coupled to said encoder and responsive to said representation and to said cycle times for providing a serialized representation defining both particular key actuation and said address; and d. storage means coupled to said permanent store memory for storing said serialized representation.
 2. The calculator system according to claim 1 wherein said encoder means provides both true and complement representations of said particular row actuation.
 3. The calculator system according to claim 2 wherein said storage means comprises a sequentially addressed memory having columns sequentially strobed by subcycle times of said cycle times.
 4. The calculator system according to claim 3 wherein each row of said sequentially addressed memory has separate input and separate output lines and each column has separate read/write lines strobed by said subcycle times.
 5. The calculator system according to claim 4 wherein said means responsive to said representations include means responsive to both said true and complement representations for generating an enable signal for enabling said serialized representation to enter said storage means.
 6. The calculator system according to claim 5 wherein said means responsive to said true and complement representations provides said enable signal only when said true representation is the complement of said complement representation. 